4571 Datasheet, PDF (8/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
PORT BLOCK DIAGRAM
Register Y
Decoder
Skip decision
SZD instruction
(Note 3) _FR1i
CLD instruction
SD instruction
RD instruction
S
RQ
(Note 1)
D0-D3 (Note 2)
(Note 1)
Register Y
Decoder
Skip decision
SZD instruction
CLD
instruction
SD instruction
S
W50
RD instruction
RQ
0
W23
Timer 1 underflow signal ⁰
1
Timer 2 underflow signal
1
1/2
W52
Clock input for timer 1
0
event count
1
(Note 1)
D4/CNTR0 (Note 2)
(Note 1)
W10
W11
(Note 4)
Key-on wakeup input
Edge detection
circuit
(Note 3)
IAP0 instruction
Register A
Ai
K0i (Note 3) Pull-up transistor
PU0i
(Note 3)
Ai
D
OP0A instruction T Q
(Note 1)
P00-P03 (Note 2)
(Note 1)
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. i represents bits 0 to 3.
4. A falling edge of port input is detected.
Fig 3. Port block diagram (1)
Rev.1.02 May 25, 2007 Page 8 of 124
REJ03B0179-0102