4571 Datasheet, PDF (28/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
Division circuit ^MR3,MR2
System clock (STCK)
11
Instruction clock
Divided by 8
(INSTCK)
10
Divided by 4
Internal clock
PA1
01
generating circuit
0
Divided by 2
(divided by 3)
00
XIN
1/4
1
PA0
Prescaler (8)
ORCLK
PWMOUT
ORCLK
STCK
CNTR0IN
W11, W10
00
01
10
11
W12
(Note 1)
INT0SNC S Q
I10
W13
R
(TABPS)
Reload register RPS (8)
(TPSAB)
(TPSAB)
(TPSAB)
Register B Register A
(TABPS)
W53
0
Timer 1 (8)
T1F
1
(TAB1)
Reload register R1 (8)
(T1AB) (TR1AB) (T1AB)
(T1AB)
Register B Register A
(TAB1)
Timer 1
interrupt
T1UDF
T1UDF
PWMOUT
ORCLK
STCK
T1UDF
W21, W20
00
01
10
Timer 2 (8)
T2F
11
W22
Reload register R2 (8)
(T2AB)
(TAB2)
(T2AB)
(T2AB)
(TAB2)
Register B Register A
Timer 2
interrupt
T2UDF
P20/INT0
I13
D4/CNTR0
I12
One-sided edge I11
0
detection circuit
0
1
Both edges
1
detection circuit
W50
0
Port D4 output W23
0
1
1/2
W52
1
0
CNTR0IN
1
T1UDF
T2UDF
INTSNC
PWMOUT: PWM signal (output from timer 3)
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: Timer 1 count start synchronous circuit is synchronized with the valid edge of
INT pin selected by bits 1 (I11) and 2 (I12) of register I1.
Fig 31. Timers structure (1)
Rev.1.02 May 25, 2007 Page 28 of 124
REJ03B0179-0102