4571 Datasheet, PDF (41/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(4) Internal state at reset
Figure 43 shows internal state at reset (they are the same after
system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure 43 are undefined, so set
the initial value to them.
• Program counter (PC)
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE)
• Power down flag (P)
• External 0 interrupt request flag (EXF0)
• External 1 interrupt request flag (EXF1)
• Interrupt control register V1
• Interrupt control register V2
• Interrupt control register I1
• Interrupt control register I2
• Timer 1 interrupt request flag (T1F)
• Timer 2 interrupt request flag (T2F)
• Timer 3 interrupt request flag (T3F)
• Watchdog timer flags (WDF1, WDF2)
• Watchdog timer enable flag (WEF)
• Timer control register PA
• Timer control register W1
• Timer control register W2
•Timer control register W3
• Timer control register W5
• Clock control register MR
• Key-on wakeup control register K0
• Key-on wakeup control register K1
• Key-on wakeup control register K2
• Key-on wakeup control register L1
• Pull-up control register PU0
• Pull-up control register PU1
• Pull-up control register PU2
• Port output structure control register FR0
• Port output structure control register FR1
• Carry flag (CY)
• Register A
• Register B
• Register D
• Register E
• Register X
• Register Y
• Register Z
• Stack pointer (SP)
00000000000000
0 (Interrupt disabled)
0
0
0
0 0 0 0 (Interrupt disabled)
0 0 0 0 (Interrupt disabled)
0000
0000
0
0
0
0
1
0 0 (Prescaler stopped)
0 0 0 0 (Timer 1 stopped)
0 0 0 0 (Timer 2 stopped)
0 0 0 0 (Timer 3 stopped)
0000
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0000
0000
×××
××××××××
0000
0000
××
111
Fig 43. Internal state at reset
“X” represents undefined.
Rev.1.02 May 25, 2007 Page 41 of 124
REJ03B0179-0102