4571 Datasheet, PDF (123/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
Voltage drop detection circuit characteristics
Table 29 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
VRST-
Detection voltage
(reset occurs) (Note 1)
Ta = 25°C
−20°C≤ Ta < 0°C
1.65
V
1.6
2.2
0°C≤ Ta < 50°C
1.3
2.1
50°C≤ Ta ≤ 85°C
1.1
1.8
VRST+
Detection voltage
(reset release) (Note 2)
Ta = 25°C
−20°C≤ Ta < 0°C
1.75
V
1.7
2.3
0°C≤ Ta < 50°C
1.4
2.2
50°C≤ Ta ≤ 85°C
1.2
1.9
VINT
Detection voltage
Ta = 25°C
(Interrupt occurs) (Note 3)
−20°C≤ Ta < 0°C
1.85
V
1.8
2.4
0°C≤ Ta < 50°C
1.5
2.3
50°C≤ Ta ≤ 85°C
1.3
2.2
VRST+ −VRST- Detection voltage hysteresis
0.1
V
IRST
Voltage drop detection circuit
VDD = 5V
operation current (Note 4)
VDD = 3V
40
80
µA
20
40
VDD = 1.65V
7
15
TRST
Detection time (Note 5)
VDD → (VRST- −0.1V)
0.2
1.2
ms
Note 1.The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
Note 2.The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset
occurs.
Note 3.When the supply voltage goes lower than the detection voltage (VINT), the voltage drop detection circuit interrupt request flag
(VDF) is set to “1“.
Note 4.IRST is added to IDD (power current).
Note 5.The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V].
Basic timing diagram
Machine cycle
Mi
Parameter
Pin name
System clock
STCK
Mi + 1
Port output
Port input
Interrupt input
D0 to D4
P00 to P03
P10 to P13
P20, P21
P30, P31, C
D0 to D4
P00 to P03
P10 to P13
P20, P21
P30, P31, K
INT0, INT1
Rev.1.02 May 25, 2007 Page 123 of 124
REJ03B0179-0102