4571 Datasheet, PDF (64/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
Timer control register PA
PA1 Prescaler count source selection bit
PA0 Prescaler control bit
at reset : 002
at RAM back-up : 002
0 Instruction clock (INSTCK)
1 Instruction clock divided by 4 (INSTCK)/4
0 Stop (state initialized)
1 Operating
W
TPAA
Timer control register W1
at reset : 00002
at RAM back-up : state retained
W13
Timer 1 count auto-stop circuit selection bit
(Note 2)
W12 Timer 1 control bit
W11
Timer 1 count source selection bits
W10
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
0 Stop (state retained)
1 Operating
W11 W10
Count source
0 0 PWM output (PWMOUT)
0 1 Prescaler output (ORCLK)
1 0 System clock (STCK)
1 1 CNTR0 input
R/W
TAW1/TW1A
Timer control register W2
W23 CNTR0 pin function selection bit
W22 Timer 2 control bit
W21
Timer 2 count source selection bits
W20
at reset : 00002
at RAM back-up : state retained
0 Timer 1 underflow signal divided by 2 output
1 Timer 2 underflow signal divided by 2 output
0 Stop (state retained)
1 Operating
W21 W20
Count source
0 0 PWM output (PWMOUT)
0 1 Prescaler output (ORCLK)
1 0 System clock (STCK)
1 1 Timer 1 underflow signal (T1UDF)
R/W
TAW2/TW2A
Timer control register W3
W33 CNTR1 pin output control bit
W32
PWM signal
“H” interval expansion function control bit
W31 Timer 3 control bit
W30 Timer 3 count source selection bit
at reset : 00002
at RAM back-up : 00002
0 CNTR1 pin output invalid
1 CNTR1 pin output valid
0 PWM signal “H” interval expansion function invalid
1 PWM signal “H” interval expansion function valid
0 Stop (state retained)
1 Operating
0 XIN input
1 Prescaler output/2
R/W
TAW3/TW3A
Timer control register W5
at reset : 00002
at RAM back-up : state retained
R/W
TAW5/TW5A
W53
Timer 1 count start synchronous circuit
selection bit (Note 3)
0 Count start synchronous circuit not selected
1 Count start synchronous circuit selected
W52 CNTR0 pin input count edge selection bit
0 Falling edge
1 Rising edge
W51
CNTR 1 pin output auto-control circuit
selection bit
0 Output auto-control circuit not selected
1 Output auto-control circuit selected
W50 D4/CNTR0 pin function selection bit
0 D4 (I/O) / CNTR0 (input)
1 D4 (input) /CNTR0 (I/O)
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is
selected (W53 =“1”).
Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”).
Rev.1.02 May 25, 2007 Page 64 of 124
REJ03B0179-0102