4571 Datasheet, PDF (19/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register V1 to
register A.
• Interrupt control register V2
The voltage drop detection circuit interrupt enable bit and timer 3
interrupt enable bit are assigned to register V2. Set the contents
of this register through register A with the TV2A instruction. The
TAV2 instruction can be used to transfer the contents of register
V2 to register A.
Table 13 Interrupt control registers
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 External 1 interrupt enable bit
V10 External 0 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
0 Interrupt disabled (SNZT2 instruction is valid)
1 Interrupt enabled (SNZT2 instruction is invalid)
0 Interrupt disabled (SNZT1 instruction is valid)
1 Interrupt enabled (SNZT1 instruction is invalid)
0 Interrupt disabled (SNZ1 instruction is valid)
1 Interrupt enabled (SNZ1 instruction is invalid)
0 Interrupt disabled (SNZ0 instruction is valid)
1 Interrupt enabled (SNZ0 instruction is invalid)
R/W
TAV1/TV1A
Interrupt control register V2
at reset : 00002
at RAM back-up : 00002
V23 Voltage drop detector interrupt enable bit
0 Interrupt disabled (SNZVD instruction is valid)
1 Interrupt enabled (SNZVD instruction is invalid)
V22 Not used
0
This bit has no function, but read/write is enabled.
1
V21 Not used
0
This bit has no function, but read/write is enabled.
1
V20 Timer 3 interrupt enable bit
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid)
Note 1.“R” represents read enabled, and “W” represents write enabled.
R/W
TAV2/TV2A
Rev.1.02 May 25, 2007 Page 19 of 124
REJ03B0179-0102