4571 Datasheet, PDF (32/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with two timer 3 reload
registers (R3L, R3H). Data can be set simultaneously in timer 3
and the reload register R3L with the T3AB instruction. Data can
be set in the reload register R3H with the T3HAB instruction.
The contents of reload register R3L set with the T3AB
instruction can be set to timer 3 again with the T3R3L
instruction. Data can be read from timer 3 with the TAB3
instruction.
Stop counting and then execute the T3AB or TAB3 instruction to
read or set timer 3 data.
When executing the T3HAB instruction to set data to reload
register R3H while timer 3 is operating, avoid a timing when
timer 3 underflows.
Timer 3 starts counting after the following process;
(1) set data in timer 3
(2) set count source by bit 0 of register W3, and
(3) set the bit 1 of register W3 to “1.”
When a value set in reload register R3L is n and a value set in
reload register R3H is m, timer 3 divides the count source signal
by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255).
<Bit 3 of register W3 = “0” (CNTR1 pin output invalid)>
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the
timer 3 interrupt request flag (T3F) is set to “1,” new data is
loaded from reload register R3L, and count continues (auto-
reload function).
<Bit 3 of register W3 = “1” (CNTR1 pin output valid)>
Timer 3 generates the PWM signal of the “L” interval set as
reload register R3L, and the “H” interval set as reload register
R3H. The PWM (PWMOD) signal generated by timer 3 is output
from CNTR1 pin.
When bit 2 of register W3 is set to “1” at this time, timer 3
extends the interval set to reload register R3H for a half period of
count source. When a value set in reload register R3H is n, timer
3 divides the count source signal by m + 1.5 (m = 1 to 255).
When this function is used, set “1” or more to reload register
R3H.
When bit 1 of register W5 is set to “1”, the PWM signal output to
CNTR1 pin is switched to valid/invalid each timer 1 underflow.
However, when timer 3 is stopped, this function is canceled.
Even when bit 1 of a register W3 is cleared to “0” in the “H”
interval of PWM signal, timer 3 does not stop until it next timer 3
underflow.
When bit 1 of register W3 is cleared to “0” in order to stop timer
3 while the PWM output is used, avoid a timing when timer 3
underflows.
If these timings overlap, a hazard may occur in a CNTR1 output
waveform.
(6) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which
synchronizes the input of INT0 pin, and can start the timer count
operation.
Timer 1 count start synchronous circuit function can be selected
after timer 1 control by INT0 pin is enabled by setting the bit 0 of
register I1 to “1” and its function is selected by setting the bit 3
of register W5 to “1”.
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to timer
by inputting valid waveform to INT0 pin.
The valid waveform of INT0 pin to set the count start
synchronous circuit is the same as the external interrupt activated
condition.
Once set, the count start synchronous circuit is cleared by
clearing the bit I10 to “0” or system reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1
underflow.
(7) Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop
timer 1 automatically by the timer 1 underflow when the count
start synchronous circuit is used.
The count auto-stop circuit is valid by setting the bit 3 of register
W1 to “1”. It is cleared by the timer 1 underflow and the count
source to timer 1 is stopped.
This function is valid only when the timer 1 count start
synchronous circuit is selected.
(8) Timer input/output pin (D4/CNTR0)
CNTR0 pin is used to input the timer 1 count source and output
the timer 1 or timer 2 underflow signal/2.
The D4/CNTR0 pin function can be selected by bit 0 of register
W5.
The output signal can be selected by bit 0 of register W2.
When the CNTR0 input is selected for timer 1 count source,
timer 1 counts the falling or rising waveform of CNTR0 input.
The count edge is selected by bit 2 of register W5.
(9) PWM signal output function (C/CNTR1, timer 1,
timer 2)
The C/CNTR1 pin is also used to output the PWM signal
generated by timer 3.
When the bit 3 of register W3 is set to “1”, the PWM signal can
be output from the C/CNTR1 pin. In this time, set the output
latch of port C to “1.”
(10)Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the
skip instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control register V1, V2 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
Rev.1.02 May 25, 2007 Page 32 of 124
REJ03B0179-0102