4571 Datasheet, PDF (23/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(3) External interrupt control registers
(1) Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt. Set the contents of this register through register A
with the TI1A instruction. The TAI1 instruction can be used
to transfer the contents of register I1 to register A.
(2) Interrupt control register I2
Register I2 controls the valid waveform for the external 1
interrupt. Set the contents of this register through register A
with the TI2A instruction. The TAI2 instruction can be used
to transfer the contents of register I2 to register A.
Table 15 External interrupt control register
Interrupt control register I1
I13 INT0 pin input control bit (Note 2)
I12
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
I11 INT0 pin edge detection circuit control bit
I10
INT0 pin
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
TAI1/TI1A
0 INT0 pin input disabled
1 INT0 pin input enabled
0
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
1
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
0 One-sided edge detected
1 Both edges detected
0 Timer 1 disabled
1 Timer 1 enabled
Interrupt control register I2
at reset : 00002
at RAM back-up : state retained
R/W
TAI2/TI2A
I23 INT1 pin input control bit (Note 3)
0 INT0 pin input disabled
1 INT0 pin input enabled
I22
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
0
Falling waveform (“L” level of INT0 pin is recognized with the SNZI1
instruction)/“L” level
1
Rising waveform (“H” level of INT0 pin is recognized with the SNZI1
instruction)/“H” level
I21 INT1 pin edge detection circuit control bit
0 One-sided edge detected
1 Both edges detected
I20 Not used
0
This bit has no function, but read/write is enabled.
1
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set.
Rev.1.02 May 25, 2007 Page 23 of 124
REJ03B0179-0102