4571 Datasheet, PDF (63/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
CONTROL REGISTERS
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 External 1 interrupt enable bit
V10 External 0 interrupt enable bit
Interrupt control register V2
V23 Voltage drop detector interrupt enable bit
V22 Not used
V21 Not used
V20 Timer 3 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
0 Interrupt disabled (SNZT2 instruction is valid)
1 Interrupt enabled (SNZT2 instruction is invalid)
0 Interrupt disabled (SNZT1 instruction is valid)
1 Interrupt enabled (SNZT1 instruction is invalid)
0 Interrupt disabled (SNZ1 instruction is valid)
1 Interrupt enabled (SNZ1 instruction is invalid)
0 Interrupt disabled (SNZ0 instruction is valid)
1 Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
at RAM back-up : 00002
0 Interrupt disabled (SNZVD instruction is valid)
1 Interrupt enabled (SNZVD instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV1/TV1A
R/W
TAV2/TV2A
Interrupt control register I1
I13 INT0 pin input control bit (Note 2)
I12
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
I11 INT0 pin edge detection circuit control bit
I10
INT0 pin
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
TAI1/TI1A
0 INT0 pin input disabled
1 INT0 pin input enabled
0
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
1
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
0 One-sided edge detected
1 Both edges detected
0 Timer 1 disabled
1 Timer 1 enabled
Interrupt control register I2
at reset : 00002
at RAM back-up : state retained
R/W
TAI2/TI2A
I23 INT1 pin input control bit (Note 3)
0 INT0 pin input disabled
1 INT0 pin input enabled
I22
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
0
Falling waveform (“L” level of INT0 pin is recognized with the SNZI1
instruction)/“L” level
1
Rising waveform (“H” level of INT0 pin is recognized with the SNZI1
instruction)/“H” level
I21 INT1 pin edge detection circuit control bit
0 One-sided edge detected
1 Both edges detected
I20 Not used
0
This bit has no function, but read/write is enabled.
1
Note 1.”R” represents read enabled, and “W” represents write enabled.
Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set.
Rev.1.02 May 25, 2007 Page 63 of 124
REJ03B0179-0102