4571 Datasheet, PDF (29/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
XIN
ORCLK
Register B Register A
W30
0
1/2 1
(T3HAB)
Reload Register R3H (8)
Timer 3 (8)
(Note 1)
Reload control circuit
W32
“H” interval expansion
1
W31
(T3R3L)
0
Reload Register R3L (8)
(T3AB)
(TAB3)
(T3AB)
(T3AB)
(TAB3)
Register B Register A
TQ
PWMOD
R
W33
T3F
Timer 3
interrupt
PWMOUT
C/CNTR1
PWMOD
Port C output
QD
W12 R T
T1UDF
W51
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
(Note 2)
SQ
WDF1
WRST instruction _R
Reset signal
(Note 4)
DWDT instruction
+
WRST instruction
SQ
WEF
R
(Note 3)
T2UDF: Timer 2 underflow signal
ORCLK: Prescaler output
DQ
Watchdog reset
signal
T R ^{reset signal}
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: When the CNTR1 output function is valid (W33=“1”), the value is auto-reloaded alternately from reload register
R3L and R3H every timer 3 underflow.
When the CNTR1 function is invalid (W33=“0”), the value is auto-reloaded from reload register R3L only.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 32. Timers structure (2)
Rev.1.02 May 25, 2007 Page 29 of 124
REJ03B0179-0102