4571 Datasheet, PDF (44/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
RAM BACK-UP MODE
The 4571 Group has the RAM back-up mode.
When the POF instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
The POF instruction is equal to the NOP instruction when the
EPOF instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit
and states at RAM back-up mode, current dissipation can be
reduced without losing the contents of RAM.
Table 19 shows the function and states retained at RAM back-up.
Figure 47 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF instruction and
POF instruction continuously, the CPU starts executing the
program from address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed, or
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
Table 19 Functions and states retained at RAM back-up
Function
RAM back-up
Program counter (PC), stack pointer (SP)
(Table 2), carry flag (CY), registers A, B
×
Contents of RAM
O
Interrupt control registers V1, V2
×
Interrupt control registers I1, I2
O
Clock control register MR
×
Timer 1, Timer 2, Timer 3 function
(Note 3)
Watchdog timer function
× (Note 4)
Timer control registers PA, W3
×
Timer control registers W1, W2, W5
O
Voltage drop detection circuit
(Note 5)
Port level
(Note 6)
Key-on wakeup control registers K0 to K2, L1
O
Pull-up control registers PU0 to PU2
O
Port output structure control registers FR0, FR1
O
External interrupt request flags (EXF0, EXF1)
×
Timer interrupt request flags (T1F, T2F, T3F)
(Note 3)
Voltage drop detection circuit interrupt request
flag (VDF)
×
Interrupt enable flag (INTE)
×
Watchdog timer flags (WDF1, WDF2)
× (Note 4)
Watchdog timer enable flag (WEF)
× (Note 4)
Note 1.“O” represents that the function can be retained, and “×”
represents that the function is initialized.
Registers and flags other than the above are undefined at
RAM back-up, and set an initial value after returning.
Note 2.The stack pointer (SP) points the level of the stack register
and is initialized to “7” at RAM back-up.
Note 3.The state of the timer is undefined.
Note 4.Initialize the watchdog timer flag WDF1 with the WRST
instruction, and then set the system to be in the RAM
back-up mode.
Note 5.The voltage drop detection circuit is invalid.
Note 6.C/CNTR pin outputs “L” level. Other ports retain their
output levels.
Rev.1.02 May 25, 2007 Page 44 of 124
REJ03B0179-0102