4571 Datasheet, PDF (7/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
CONNECTIONS OF UNUSED PINS
Table 7 Port function
Pin
D0−D3
P30, P31
D4/CNTR0
P00−P03,
P10−P13
P20/INT0
P21/INT1
C/CNTR1
K
Connection
Open.
Connect to VSS.
Connect to VDD.
Open.
Connect to VSS.
Connect to VDD.
Open.
Connect to VSS.
Connect to VDD.
Open.
Connect to VSS.
Connect to VDD.
Open.
Connect to VSS.
Connect to VSS.
Connect to VDD.
Output structure
N-channel open-drain
CMOS
N-channel open-drain
CMOS
N-channel open-drain
CMOS
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
CMOS
CMOS
−
−
Pull-up
transistor
−
−
−
−
−
−
−
−
−
OFF
ON
OFF
ON/OFF
OFF
ON
OFF
ON/OFF
−
−
−
−
Usage condition
Key-on wakeup
−
−
−
−
−
−
−
−
−
Invalid
Invalid
Invalid
Valid/Invalid
Invalid
Invalid
Invalid
Valid/Invalid
−
−
Invalid
Valid/Invalid
Value of
output latch
0/1
0/1
0/1
0
1
1
0/1
0/1
1
0/1
1
0/1
1
0/1
1
0/1
1
0/1
0
−
−
Others
(Note 1)
−
−
−
−
−
(Notes 1, 2)
(Note 2)
(Note 2)
(Note 1)
−
−
−
(Notes 1, 3)
(Note 3)
(Note 3)
(Note 3)
−
(Note 4)
−
−
Note 1.If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed when the output latch is 1, the supply voltage may be
increased in the instruction execution cycle by the through current.
Note 2.Do not select the CNTR0 input as the timer 1 count source. (W11 W10≠11)
Note 3.Set the input of INT0 pin or INT1 pin to be disabled. (I13=0, I23=0)
Note 4.Set the output of the CNTR1 pin to be invalid. (W33=0)
(Note when connecting to VSS or VDD)
Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Rev.1.02 May 25, 2007 Page 7 of 124
REJ03B0179-0102