4571 Datasheet, PDF (6/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
PORT FUNCTION
Table 5
Port
Port D
Port function
Pin
D0−D3
D4/CNTR0
Input
Output
I/O
(5)
Output
structure
N-channel
open-drain/
CMOS
N-channel
open-drain
Port P0
Port P1
Port P2
Port P3
Port C
Port K
P00
P01
P02
P03
P10
P11
P12
P13
P20/INT0
P21/INT1
P30
P31
C/CNTR1
K
I/O N-channel
(4) open-drain
I/O N-channel
(4) open-drain
I/O
(2)
I/O
(2)
Output
(1)
Input
(1)
N-channel
open-drain
N-channel
open-drain/
CMOS
CMOS
-
I/O unit
1 bit
4 bits
4 bits
2 bits
2 bits
1 bit
1 bit
Control
instructions
SD, RD
SZD, CLD
Control
registers
FR1
W1
W2
W5
OP0A
PU0
IAP0
K0
Remark
Programmable output
structure selection function
−
Programmable pull-up and
key-on wakeup function
OP1A
PU1
IAP1
K1
Programmable pull-up and
key-on wakeup function
OP2A
IAP2
OP3A
IAP3
RCP
SCP
IAK
PU2
K2, I1, I2, L1
FR0
Programmable pull-up and
key-on wakeup function
Programmable output
structure selection function
W1, W3, W5 −
K2
Programmable key-on
wakeup function
DEFINITION OF CLOCK AND CYCLE
• Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external input
• System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR.
• Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
• Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Table 6 Table Selection of system clock
Register MR
MR3 MR2
System clock
Operation mode
1
1 f(STCK) = f(XIN)/8 Frequency divided by 8 mode
1
0 f(STCK) = f(XIN)/4 Frequency divided by 4 mode
0
1 f(STCK) = f(XIN)/2 Frequency divided by 2 mode
0
0 f(STCK) = f(XIN) Frequency through mode
Note 1.The frequency divided by 8 is selected after system is
released from reset.
Rev.1.02 May 25, 2007 Page 6 of 124
REJ03B0179-0102