4571 Datasheet, PDF (20/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt
enable bits (V10−V13, V20, V23), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles only when the three interrupt
conditions are satisfied on execution of other than one-cycle
instructions (Refer to Figure 22).
When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
System clock
(STCK)
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
Interrupt enable
flag (INTE)
EI instruction execution
cycle
Interrupt enabled state
External 0,
External 1
interrupt
INT0
INT1
EXF0
EXF1
Timer 1
Timer 2 ^T1F
Timer 3 ^T2F
interrupt ^T3F
Voltage drop
detection circuit VDF
interrupt
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time
when each interrupt activated condition is satisfied.
Interrupt activated
condition is satisfied.
Interrupt disabled state
Retaining level of system
clock for 4 periods or more
is necessary.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
The program starts
from the interrupt
address.
Fig 22. Interrupt sequence
Rev.1.02 May 25, 2007 Page 20 of 124
REJ03B0179-0102