4571 Datasheet, PDF (24/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(4) Notes on interrupts
(1) Bit 3 of register I1
When the input of the P20/INT0 pin is controlled with the
bit 3 of register I1 in software, be careful about the
following notes.
• Depending on the input state of the P20/INT0 pin, the external
0 interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 24) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 24).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
24).
(3) Bit 2 of register I1
When the interrupt valid waveform of the P20/INT0 pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
• Depending on the input state of the P20/INT0 pin, the external
1 interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 26) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 26).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
26).
•••
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
•••
; (×××02)
; The SNZ0 instruction is valid ...... (1)
; (1×××2)
; Control of INT0 pin input is changed
...................................................... (2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
...................................................... (3)
×: these bits are not used here.
•••
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
•••
; (×××02)
; The SNZ0 instruction is valid ......(1)
; (1×××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
.......................................................(3)
×: these bits are not used here.
Fig 24. External 0 interrupt program example-1
Fig 26. External 0 interrupt program example-3
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM
back-up mode is selected and the input of INT0 pin is
disabled, be careful about the following notes.
• When the INT0 pin input is disabled (register I13 = “0”), set
the key-on wakeup of INT0 pin to be invalid (register L10 =
“0”) before system enters to the RAM back-up mode. (refer to
(1) in Figure 25).
•••
LA 0
TL1A
DI
EPOF
POF
•••
; (×××02)
; INT0 key-on wakeup disabled .....(1)
; RAM back-up
×: these bits are not used here.
Fig 25. External 0 interrupt program example-2
Rev.1.02 May 25, 2007 Page 24 of 124
REJ03B0179-0102