4571 Datasheet, PDF (67/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
INSTRUCTIONS
Each instruction is described as follows;
1. Index list of instruction function
2. Machine instructions (index by alphabet)
3. Machine instructions (index by function)
4. Instruction code table
SYMBOL
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Symbol
Contents
Symbol
Contents
A
Register A (4 bits)
T1F
Timer 1 interrupt request flag
B
Register B (4 bits)
T2F
Timer 2 interrupt request flag
DR
Register DR (3 bits)
T3F
Timer 3 interrupt request flag
E
Register E (8 bits)
WDF1
Watchdog timer flag
V1
Interrupt control register V1 (4 bits)
WEF
Watchdog timer enable flag
V2
Interrupt control register V2 (4 bits)
INTE
Interrupt enable flag
I1
Interrupt control register I1 (4 bits)
EXF0
External 0 interrupt request flag
I2
Interrupt control register I2 (4 bits)
EXF1
External 1 interrupt request flag
PA
Timer control register PA (2 bits)
VDF
Voltage drop detection circuit interrupt request flag
W1
Timer control register W1 (4 bits)
P
Power down flag
W2
Timer control register W2 (4 bits)
D
Port D (5 bits)
W3
Timer control register W3 (4 bits)
P0
Port P0 (4 bits)
W5
Timer control register W5 (4 bits)
P1
Port P1 (4 bits)
MR
Clock control register MR (4 bits)
P2
Port P2 (2 bits)
K0
Key-on wakeup control register K0 (4 bits)
P3
Port P3 (2 bits)
K1
Key-on wakeup control register K1 (4 bits)
K2
Key-on wakeup control register K2 (4 bits)
x
Hexadecimal variable
L1
Key-on wakeup control register L1 (4 bits)
y
Hexadecimal variable
PU0
Pull-up control register PU0 (4 bits)
z
Hexadecimal variable
PU1
Pull-up control register PU1 (4 bits)
p
Hexadecimal variable
PU2
Pull-up control register PU2 (4 bits)
n
Hexadecimal constant
FR0
Port output structure control register FR0 (4 bits)
i
Hexadecimal constant
FR1
Port output structure control register FR1 (4 bits)
j
Hexadecimal constant
X
Register X (4 bits)
Y
Register Y (4 bits)
A3 A2 A1 A0 Binary notation of hexadecimal variable A
(same for others)
Z
Register Z (2 bits)
DP
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
←
Direction of data movement
()
Contents of registers and memories
PC
Program counter (14 bits)
−
Negate, Flag unchanged after executing instruction
PCH
High-order 7 bits of program counter
M (DP)
RAM address pointed by the data pointer
PCL
Low-order 7 bits of program counter
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
SK
Stack register (14 bits × 8)
SP
Stack pointer (3 bits)
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0 in page
p6 p5 p4 p3 p2 p1 p0
CY
Carry flag
RPS
Prescaler reload register (8 bits)
C
Hex. C + Hex. number x (also same for others)
R1L
Timer 1 reload register (8 bits)
+
R2
Timer 2 reload register (8 bits)
x
R3L
Timer 3 reload register (8 bits)
?
Decision of state shown before “?”
R3H
Timer 3 reload register (8 bits)
←→
Data exchange between a register and memory
PS
Prescaler
T1
Timer 1
AND
Logical multiplication
T2
Timer 2
OR
Logical addition
T3
Timer 3
Note 1.The 4571 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased
by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if
the TABP p, RT, or RTS instruction is skipped.
Rev.1.02 May 25, 2007 Page 67 of 124
REJ03B0179-0102