4571 Datasheet, PDF (58/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(12)Prescaler
Stop prescaler counting and then execute the TABPS instruction
to read its data.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
(13)Timer count source
Stop timer 1, 2 or 3 counting to change its count source.
(14)Reading the count value
Stop timer 1, 2 or 3 counting and then execute the TAB1, TAB2
or TAB3 instruction to read its data.
(15)Writing to the timer
Stop timer 1, 2 or 3 counting and then execute the T1AB, T2AB,
T3AB or T3R3L instruction to write data to timer.
(16)Writing to reload register
In order to write a data to the reload register R1 while the timer 1
is operating, execute the TR1AB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R3H while the timer
3 is operating, execute the T3HAB instruction except a timing of
the timer 3 underflow.
(17)PWM signal
If the timer 3 count stop timing and the timer 3 underflow timing
overlap during output of the PWM signal, a hazard may occur in
the PWM output waveform.
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R3H.
Set the port C output latch to “0” to output the PWM signal from
C/CNTR1 pin.
(18)Prescaler, timer 1, timer 2 and timer 3 count start
timing and count time when operation starts
Count starts from the first rising edge of the count source (2) in
Figure 61 after prescaler and timer operations start (1) in Figure
61.
Time to first underflow (3) in Figure 61 is shorter (for up to 1
period of the count source) than time among next underflow (4)
in Figure 61 by the timing to start the timer and count source
operations after count starts.
When selecting CNTR0 input as the count source of timer 1,
timer 1 operates synchronizing with the count edge (falling edge
or rising edge) of CNTR0 input selected by software.
(19)Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction
continuously, and clear the WEF flag to “0” to stop the
watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at
the RAM back-up mode.
• When using the watchdog timer and the RAM back-up mode,
initialize the WDF1 flag with the WRST instruction just
before the microcomputer enters the RAM back-up state.
Also, set the NOP instruction after the WRST instruction, for
the case when a skip is performed with the WRST instruction.
(20)External clock
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating
condition).
Also, note that the RAM back-up mode (POF instruction) cannot
be used when using the external clock.
(21)QzROM
(1) Be careful not to apply overvoltage to MCU. The contents
of QzROM may be overwritten because of overvoltage.
Take care especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not
perform the writing test to user ROM area after the
assembly process though the QzROM writing test is
performed enough before the assembly process. Therefore, a
writing error of approx.0.1 % may occur. Moreover, please
note the contact of cables and foreign bodies on a socket,
etc. because a writing environment may cause some writing
errors.
(22)Notes On ROM Code Protect (QzROM product
shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in
the mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016” and “FF16” can not be
accepted.
(2)
Count source
Count source
(When falling edge of
CNTR0 input is selected)
Timer 1 value 3 2 1 0 3 2 1 0 3 2
Timer 1 underflow signal
(3)
(4)
(1) Timer start
Fig 61. Timer count start timing and count time when
operation starts
Rev.1.02 May 25, 2007 Page 58 of 124
REJ03B0179-0102