4571 Datasheet, PDF (18/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 20).
• Program counter (PC)
An interrupt address is set in program counter. The address to
be executed when returning to the main routine is
automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared
to “0” (the voltage drop detection circuit interrupt request flag
is excluded)
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is
executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an
interrupt address. Use the RTI instruction to return from an
interrupt service routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed just
before the RTI instruction, interrupts are enabled after returning
the main routine. (Refer to Figure 19)
• Program counter (PC)
Each interrupt address
• Stack register (SK)
The address of main routine to be
executed when returning
• Interrupt enable flag (INTE)
0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source)
0 (excluding voltage drop detection interrupt request flag)
• Data pointer, carry flag, registers A and B, skip flag
Stored in the interrupt stack register (SDP)
automatically
Fig 20. Internal state when interrupt occurs
Activated
condition
Request flag
(state retained)
Enable bit
when supply voltage
goes lower than
specified value
VDF
V23
Enable flag
Address E
in page 1
INT0 pin interrupt
waveform input
EXF0
V10
Address 0
in page 1
Main
routine
Interrupt
occurs
Interrupt
service routine
INT1 pin interrupt
waveform input
EXF1
V11
Timer 1
underflow
T1F
V12
Timer 2
underflow
T2F
V13
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
EI
RTI
Interrupt is
enabled
Timer 3
underflow
T3F
V20
Fig 21. Interrupt system diagram
INTE
Address 8
in page 1
: Interrupt enabled state
: Interrupt disabled state
Fig 19. Program example of interrupt processing
Rev.1.02 May 25, 2007 Page 18 of 124
REJ03B0179-0102