4571 Datasheet, PDF (21/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
EXTERNAL INTERRUPTS
The 4571 Group has the external 0 interrupt and external 1
interrupt. An external interrupt request occurs when a valid
waveform is input to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Table 14 External interrupt activated conditions
Name
Input pin
Activated condition
External 0 interrupt P20/INT0
External 1 interrupt P21/INT1
When the next waveform is input to P20/INT0 pin
• Falling waveform (“H” → “L”)
• Rising waveform (“L” → “H”)
• Both rising and falling waveforms
When the next waveform is input to P21/INT1 pin
• Falling waveform (“H” → “L”)
• Rising waveform (“L” → “H”)
• Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
I21
I22
(Note 1)
P20/INT0
(Note 1)
I13
I12
Falling
0
1
Rising
L10
One-sided edge
I11
detection circuit
0
1
Both edges
detection circuit
SNZI0 instruction
EXF0
External 0
interrupt
Timer 1 count start
synchronization
circuit input
Skip
(Note 2) _L11
Level detection circuit
0
Edge detection circuit
1
Key-on wakeup input
(Note 3)
(Note 1)
P21/INT1
(Note 1)
I23
I22
Falling
0
1
Rising
L12
One-sided edge
I21
detection circuit
0
1
Both edges
detection circuit
EXF1
SNZI1 instruction
Skip
(Note 2) _L13
Level detection circuit
0
Edge detection circuit
1
(Note 3)
External 1
interrupt
Key-on wakeup input
Note 1:
This symbol represents a parasitic diode on the port.
2: When IX2= 0(X=0 or 1) is 0, “L” level is detected.
When IX2 is 1, “H” level is detected.
3: When IX2 is 0, falling edge is detected.
When IX2 is 1, rising edge is detected.
Fig 23. External interrupt circuit structure
Rev.1.02 May 25, 2007 Page 21 of 124
REJ03B0179-0102