4571 Datasheet, PDF (25/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
(4) Bit 3 of register I2
When the input of the P21/INT1 pin is controlled with the
bit 3 of register I2 in software, be careful about the
following notes.
• Depending on the input state of the P21/INT1 pin, the external
1 interrupt request flag (EXF1) may be set when the bit 3 of
register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer
to (1) in Figure 27) and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1
flag to “0” after executing at least one instruction (refer to (2)
in Figure 27).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ1 instruction (refer to (3) in Figure
27).
•••
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
•••
; (××0×2)
; The SNZ1 instruction is valid ...... (1)
; (1×××2)
; Control of INT1 pin input is changed
...................................................... (2)
; The SNZ1 instruction is executed
(EXF1 flag cleared)
...................................................... (3)
×: these bits are not used here.
• Depending on the input state of the P21/INT1 pin, the external
1 interrupt request flag (EXF1) may be set when the bit 2 of
register I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to “0” (refer
to (1) in Figure 29) and then, change the bit 2 of register I2 is
changed.
In addition, execute the SNZ1 instruction to clear the EXF1
flag to “0” after executing at least one instruction (refer to (2)
in Figure 29).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ1 instruction (refer to (3) in Figure
29).
•••
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
•••
; (××0×2)
; The SNZ1 instruction is valid ......(1)
; (1×××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ1 instruction is executed
(EXF1 flag cleared)
.......................................................(3)
×: these bits are not used here.
Fig 29. External 1 interrupt program example-3
Fig 27. External 1 interrupt program example-1
(5) Bit 3 of register I2
When the bit 3 of register I2 is cleared to “0”, the RAM
back-up mode is selected and the input of INT1 pin is
disabled, be careful about the following notes.
• When the INT1 pin input is disabled (register I23 = “0”), set
the key-on wakeup of INT1 pin to be invalid (register L20 =
“0”) before system enters to the RAM back-up mode. (refer to
(1) in Figure 28)
.
•••
LA 0
TL1A
DI
EPOF
POF
•••
; (×0××2)
; INT1 key-on wakeup disabled .....(1)
; RAM back-up
×: these bits are not used here.
Fig 28. External 1 interrupt program example-2
(6) Bit 2 of register I2
When the interrupt valid waveform of the P21/INT1 pin is
changed with the bit 2 of register I2 in software, be careful
about the following notes.
Rev.1.02 May 25, 2007 Page 25 of 124
REJ03B0179-0102