4571 Datasheet, PDF (121/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
Table 27 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
f(XIN)
f(CNTR)
tw(CNTR)
TPON
Parameter
Oscillation frequency
(with a ceramic resonator)
Oscillation frequency
(with an external clock input)
Timer external input frequency
Timer external input period
(“H” and “L” pulse width)
Power-on reset circuit valid
supply voltage rising time
(Note 1)
Conditions
Through mode
Internal frequency divided
by 2
Internal frequency divided
by 4, 8
Through mode
Internal frequency divided
by 2
Internal frequency divided
by 4, 8
CNTR0, CNTR1
CNTR0, CNTR1
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 0 → 1.8V
Min.
3/f(STCK)
Limits
Typ.
Max.
6
4.4
2.2
1.1
6
4.4
2.2
6
4.4
4.8
3.2
1.6
0.8
4.8
3.2
1.6
4.8
3.2
f(STCK)/6
100
Unit
MHz
MHz
Hz
s
µs
Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest
distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
with a ceramic resonator
f(STCK)
[MHz]
6
4.4
2.2
1.1
Recommended
operating conditions
1.8 2
2.7
4 5.5 _VDD
[V]
at external clock oscillation
f(STCK)
[MHz]
4.8
3.2
1.6
Recommended
0.8
operating conditions
1.8 2
2.7
4 5.5 _VDD
[V]
Fig 71. System clock (STCK) operating condition map
Rev.1.02 May 25, 2007 Page 121 of 124
REJ03B0179-0102