4571 Datasheet, PDF (17/126 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4571 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an
individual address (interrupt address) according to each interrupt
source. An interrupt occurs when the following 3 conditions are
satisfied.
• An interrupt activated condition is satisfied (request flag =
“1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 10 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE flag
is set to “1” with the EI instruction and disabled when INTE flag
is cleared to “0” with the DI instruction. When any interrupt
occurs, the INTE flag is automatically cleared to “0,” so that
other interrupts are disabled until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and
V2 to select the corresponding interrupt or skip instruction.
Table 11 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 12 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the
corresponding interrupt request flag is set to “1.” Each interrupt
request flag except the voltage drop detection circuit interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
The voltage drop detection circuit interrupt request flag cannot
be cleared to “0” at the state that the activated condition is
satisfied.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its
interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state
is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 10.
Table 10 Interrupt sources
Priority
level
Interrupt source
Interrupt name
Activated
condition
1 Voltage drop
when supply
detection circuit voltage goes
interrupt
lower than
specified value
2 External 0
Level change of
interrupt
INT0 pin
3 External 1
interrupt
Level change of
INT1 pin
4 Timer 1 interrupt Timer 1
underflow
5 Timer 2 interrupt Timer 2
underflow
6 Timer 3 interrupt Timer 3
underflow
Interrupt
address
Address E
in page 1
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Table 11 Interrupt request flag, interrupt enable bit
and skip instruction
Interrupt name
Interrupt
request
flag
Voltage drop
detection circuit
VDF
interrupt
External 0 interrupt EXF0
External 1 interrupt EXF1
Timer 1 interrupt T1F
Timer 2 interrupt T2F
Timer 3 interrupt T3F
Skip
Interrupt
instruction enable bit
SNZVD V23
SNZ0
V10
SNZ1
V11
SNZT1 V12
SNZT2 V13
SNZT3 V20
Table 12 Interrupt enable bit function
Interrupt enable
bit
1
0
Occurrence of
interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
Rev.1.02 May 25, 2007 Page 17 of 124
REJ03B0179-0102