PIC32MX575F256H-80I Datasheet, PDF (97/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

TABLE 4-45:
CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
B000
C1CON
31:16
15:0
—
ON
—
—
—
ABAT
REQOP<2:0>
—
SIDLE
—
BUSY
—
—
—
OPMOD<2:0>
—
—
—
CANCAP
—
—
—
DNCNT<4:0>
— 0400
0000
B010
C1CFG
31:16
—
15:0 SEG2PHTS
—
SAM
—
—
—
SEG1PH<2:0>
—
—
—
PRSEG<2:0>
—
WAKFIL
—
—
—
SEG2PH<2:0>
SJW<1:0>
BRP<5:0>
0000
0000
B020
C1INT
31:16 IVRIE
15:0 IVRIF
WAKIE
WAKIF
CERRIE SERRIE RBOVIE
CERRIF SERRIF RBOVIF
—
—
—
—
—
—
—
—
—
—
MODIE CTMRIE RBIE
TBIE 0000
—
—
—
—
MODIF CTMRIF RBIF
TBIF 0000
B030
C1VEC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
FILHIT<4:0>
—
—
—
—
—
—
—
—
— 0000
—
ICOD<6:0>
0000
31:16
—
B040 C1TREC _15:0
—
—
—
—
TEC<7:0>
—
—
—
—
—
TXBO
TXBP
RXBP TXWARN RXWARN EWARN 0000
REC<7:0>
0000
B050
C1FSTAT
31:16 FIFOIP31
15:0 FIFOIP15
FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27
FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11
FIFOIP26
FIFOIP10
FIFOIP25
FIFOIP9
FIFOIP24
FIFOIP8
FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
B060
C1RXOVF
31:16 RXOVF31
15:0 RXOVF15
RXOVF30 RXOVF29 RXOVF28 RXOVF27
RXOVF14 RXOVF13 RXOVF12 RXOVF11
RXOVF26
RXOVF10
RXOVF25
RXOVF9
RXOVF24
RXOVF8
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
B070
C1TMR
31:16
15:0
CANTS<15:0>
CANTSPRE<15:0>
0000
0000
B080
C1RXM0 ^31:16
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
B090
C1RXM1 ^31:16
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
B0A0
C1RXM2 ^31:16
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
B0B0
C1RXM3 ^31:16
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
B0C0
C1FLTCON0
31:16
15:0
FLTEN3
FLTEN1
MSEL3<1:0>
MSEL1<1:0>
FSEL3<4:0>
FSEL1<4:0>
FLTEN2
FLTEN0
MSEL2<1:0>
MSEL0<1:0>
FSEL2<4:0>
FSEL0<4:0>
0000
0000
B0D0
C1FLTCON1
31:16
15:0
FLTEN7
FLTEN5
MSEL7<1:0>
MSEL5<1:0>
FSEL7<4:0>
FSEL5<4:0>
FLTEN6
FLTEN4
MSEL6<1:0>
MSEL4<1:0>
FSEL6<4:0>
FSEL4<4:0>
0000
0000
B0E0
C1FLTCON2
31:16
15:0
FLTEN11
FLTEN9
MSEL11<1:0>
MSEL9<1:0>
FSEL11<4:0>
FSEL9<4:0>
FLTEN10
FLTEN8
MSEL10<1:0>
MSEL8<1:0>
FSEL10<4:0>
FSEL8<4:0>
0000
0000
B0F0
C1FLTCON3
31:16
15:0
FLTEN15
FLTEN13
MSEL15<1:0>
MSEL13<1:0>
FSEL15<4:0>
FSEL13<4:0>
FLTEN14
FLTEN12
MSEL14<1:0>
MSEL12<1:0>
FSEL14<4:0>
FSEL12<4:0>
0000
0000
B100
C1FLTCON4
31:16
15:0
FLTEN19
FLTEN17
MSEL19<1:0>
MSEL17<1:0>
FSEL19<4:0>
FSEL17<4:0>
FLTEN18
FLTEN16
MSEL18<1:0>
MSEL16<1:0>
FSEL18<4:0>
FSEL16<4:0:
0000
0000
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.