PIC32MX575F256H-80I Datasheet, PDF (123/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
13.0 TIMER1
Note 1: This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) in the “PIC32MX Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM⁽¹⁾
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applica-
tions and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications. The
following modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1 Additional Supported Features
• Selectable Clock Prescaler
• Timer Operation during CPU Idle and Sleep mode
• Fast Bit Manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to Function as a Real-Time Clock (RTC).
PR1
Equal
16-Bit Comparator
T1IF
Event Flag
Reset
0
1
TGATE (T1CON<7>)
TMR1
QD
Q
TSYNC (T1CON<2>)
1
Sync
0
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
SOSCI
x1
SOSCEN
Gate
Sync
10
PBCLK
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 123