PIC32MX575F256H-80I Datasheet, PDF (74/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

TABLE 4-17: DMA GLOBAL REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000
DMACON⁽¹⁾
31:16
15:0
—
ON
—
FRZ
—
—
—
—
—
SUSPEND BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3010
DMASTAT
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
DMACH<2:0>
3020
DMAADDR
31:16
15:0
DMAADDR<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
0000
0000
0000
0000
0000
0000
TABLE 4-18: DMA CRC REGISTER MAP⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3030
DCRCCON
31:16
15:0
—
—
—
—
BYTO<1:0>
—
WBO
—
—
PLEN<4:0>
BITO
—
—
—
—
CRCEN CRCAPP CRCTYP
—
—
—
—
—
—
CRCCH<2:0>
31:16
3040 DCRCDATA _15:0
DCRCDATA<31:0>
3050
DCRCXOR
31:16
15:0
DCRCXOR<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
0000
0000
0000
0000
0000