PIC32MX575F256H-80I Datasheet, PDF (89/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

TABLE 4-36:
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L,
PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
61C0
CNCON
31:16
15:0
—
ON
—
—
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
61D0
CNEN
31:16
15:0
—
CNEN15
—
CNEN14
—
CNEN13
—
CNEN12
—
—
CNEN11 CNEN10
—
CNEN9
—
CNEN8
—
CNEN7
—
CNEN6
CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16
CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0
61E0
CNPUE
31:16
—
—
—
—
—
—
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
—
CNPUE9
—
CNPUE8
—
CNPUE7
—
CNPUE6
CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16
CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
0000
0000
0000
0000
0000
TABLE 4-37:
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
61C0
CNCON
31:16
15:0
—
ON
—
—
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
61D0
CNEN
31:16
15:0
—
CNEN15
—
CNEN14
—
CNEN13
—
CNEN12
—
—
CNEN11 CNEN10
—
CNEN9
—
CNEN8
—
CNEN7
—
CNEN6
—
CNEN5
—
CNEN4
—
CNEN3
CNEN18 CNEN17 CNEN16
CNEN2 CNEN1 CNEN0
61E0
CNPUE
31:16
—
—
—
—
—
—
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
—
CNPUE9
—
CNPUE8
—
CNPUE7
—
CNPUE6
—
CNPUE5
—
CNPUE4
—
CNPUE18 CNPUE17 CNPUE16
CNPUE3 CNPUE2 CNPUE1 CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
0000
0000
0000
0000
0000