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PIC32MX575F256H-80I Datasheet, PDF (72/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers
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TABLE 4-16: ADC REGISTER MAP
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9000
AD1CON1(1)
31:16
15:0
—
ON
—
—
FRZ
SIDL
—
—
—
—
—
—
—
FORM<2:0>
—
—
—
—
—
SSRC<2:0>
CLRASAM
—
—
ASAM
—
SAMP
—
DONE
9010
AD1CON2(1)
31:16
15:0
—
VCFG2
—
VCFG1
—
VCFG0
—
OFFCAL
—
—
—
CSCNA
—
—
—
—
—
—
BUFS
—
—
—
—
SMPI<3:0>
—
—
—
BUFM
ALTS
9020
AD1CON3(1)
31:16
15:0
—
ADRC
—
—
—
—
—
—
—
—
SAMC<4:0>
—
—
—
—
—
—
ADCS<7:0>
—
—
—
9040
AD1CHS(1)
31:16
15:0
CH0NB
—
—
—
—
—
—
—
—
CH0SB<3:0>
—
—
CH0NA
—
—
—
—
—
—
—
—
—
CH0SA<3:0>
—
—
—
9060 AD1PCFG(1) 31:16
—
—
—
—
—
—
15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10
—
PCFG9
—
PCFG8
—
PCFG7
—
PCFG6
—
PCFG5
—
PCFG4
—
PCFG3
—
PCFG2
—
PCFG1
—
PCFG0
9050
AD1CSSL(1)
31:16
15:0
—
CSSL15
—
CSSL14
—
CSSL13
—
CSSL12
—
CSSL11
—
CSSL10
—
CSSL9
—
CSSL8
—
CSSL7
—
CSSL6
—
CSSL5
—
CSSL4
—
CSSL3
—
CSSL2
—
CSSL1
—
CSSL0
9070
ADC1BUF0
31:16
15:0
ADC Result Word 0 (ADC1BUF0<31:0>)
9080
ADC1BUF1
31:16
15:0
ADC Result Word 1 (ADC1BUF1<31:0>)
9090
ADC1BUF2
31:16
15:0
ADC Result Word 2 (ADC1BUF2<31:0>)
90A0
ADC1BUF3
31:16
15:0
ADC Result Word 3 (ADC1BUF3<31:0>)
90B0
ADC1BUF4
31:16
15:0
ADC Result Word 4 (ADC1BUF4<31:0>)
90C0
ADC1BUF5
31:16
15:0
ADC Result Word 5 (ADC1BUF5<31:0>)
90D0
ADC1BUF6
31:16
15:0
ADC Result Word 6 (ADC1BUF6<31:0>)
90E0
ADC1BUF7
31:16
15:0
ADC Result Word 7 (ADC1BUF7<31:0>)
90F0
ADC1BUF8
31:16
15:0
ADC Result Word 8 (ADC1BUF8<31:0>)
9100
ADC1BUF9
31:16
15:0
ADC Result Word 9 (ADC1BUF9<31:0>)
9110
ADC1BUFA
31:16
15:0
ADC Result Word A (ADC1BUFA<31:0>)
9120
ADC1BUFB
31:16
15:0
ADC Result Word B (ADC1BUFB<31:0>)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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