PIC32MX575F256H-80I Datasheet, PDF (44/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
3.3 Power Management
The PIC32MX5XX/6XX/7XX family core offers a number
of power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 27.0
“Power-Saving Features”.
3.3.2 LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32MX family uses
extensive use of local gated clocks to reduce this
dynamic power consumption.
3.4 EJTAG Debug Support
The PIC32MX5XX/6XX/7XX family core provides for
an Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard User mode and Kernel modes of
operation, the PIC32MX5XX/6XX/7XX family core pro-
vides a Debug mode that is entered after a debug
exception (derived from a hardware breakpoint, single-
step exception, etc.) is taken and continues until a
Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the
PIC32MX5XX/6XX/7XX family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
DS61156C-page 44
Preliminary
 2010 Microchip Technology Inc.