PIC32MX575F256H-80I Datasheet, PDF(227/236 Page) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

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PIC32MX575F256H-80I Datasheet, PDF (227/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

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PIC32MX5XX/6XX/7XX

APPENDIX A:

MIGRATING FROM

PIC32MX3XX/4XX TO

PIC32MX5XX/6XX/7XX

DEVICES

This appendix provides an overview of considerations

for migrating from PIC32MX3XX/4XX devices to the

PIC32MX5XX/6XX/7XX family of devices. The code

developed for the PIC32MX3XX/4XX devices can be

ported to the PIC32MX5XX/6XX/7XX devices after

making the appropriate changes outlined below.

A.1 DMA

PIC32MX5XX/6XX/7XX devices do not support

stopping DMA transfers in Idle mode.

A.3 Pin Assignments

PIC32MX5XX/6XX/7XX devices have the same pin

assignment for peripherals as PIC32MX4XX devices

with the following exceptions:

â¢ Pins associated with the UART1 and UART2

modules on PIC32MX4XX devices are now

associated with the UART1A and UART3A

modules, respectively on PIC32MX5XX/6XX/7XX

devices

â¢ Pins associated with the SPI2 module on

PIC32MX4XX devices are now associated with

the SPI2A module on PIC32MX5XX/6XX/7XX

devices

A.2 Interrupts

PIC32MX5XX/6XX/7XX devices have persistent inter-

rupts for some of the peripheral modules. This means

that the interrupt condition for these peripherals must

be cleared before the interrupt flag can be cleared.

For example, to clear a UART receive interrupt, the

user application must first read the UART Receive reg-

ister to clear the interrupt condition and then clear the

associated UxIF flag to clear the pending UART inter-

rupt. In other words, the UxIF flag cannot be cleared by

software until the UART Receive register is read.

Table A-1 outlines the peripherals and associated

interrupts that are implemented differently on

PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX

devices.

In addition, on the SPI module, the IRQ numbers for the

receive done interrupts were changed from 25 to 24

and the transfer done interrupts were changed from 24

to 25.

TABLE A-1:

Module

Input Capture

SPI

UART

ADC

PMP

PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION

DIFFERENCES

Interrupt Implementation

To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of

capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).

Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,

respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF

register to obtain the number of data to receive/transmit below the level specified by the

SRXISEL<1:0> and STXISEL<1:0> bits.

TX interrupt will be generated as soon as the UART module is enabled.

Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,

respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or

UxTXREG registers to obtain the number of data to receive/transmit below the level specified by

the URXISEL<1:0> and UTXISEL<1:0> bits.

All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.

To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)

register.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS61156C-page 227

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