PIC32MX575F256H-80I Datasheet, PDF (45/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
4.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. For detailed
information, refer to Section 3. “Memory
Organization” (DS61115) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
4.1 PIC32MX5XX/6XX/7XX Memory
Layout
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are shown in Figure 4-1, Figure 4-2 and
Figure 4-3.
4.1.1
PERIPHERAL REGISTERS
LOCATIONS
Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX
devices. Peripherals located on the PB bus are
mapped to 512-byte boundaries. Peripherals on the
FPB bus are mapped to 4-Kbyte boundaries.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 45