PIC32MX575F256H-80I Datasheet, PDF (151/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
27.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 10. “Power-Saving Features”
(DS61130) in the “PIC32MX Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a
total of nine methods and modes, organized into two
categories, that allow the user to balance power
consumption with device performance. In all of the
methods and modes described in this section, power
saving is controlled by software.
27.1 Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK and by individually disabling modules.
These methods are grouped into the following
categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
27.2 CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate.
Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers.
Peripherals continue to operate, but can
optionally be individually disabled.
• SOSC Idle mode: the system clock is derived from
the SOSC.
Peripherals continue to operate, but can
optionally be individually disabled.
• LPRC Idle mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted.
Some peripherals can operate in Sleep using
specific clock sources. This is the lowest power
mode for the device.
27.3 Power-Saving Operation
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
27.3.1 SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
eral module sections for descriptions of behavior in
Sleep.
Sleep mode includes the following characteristics:
• The CPU is Halted.
• The system clock source is typically shut down.
See Section 27.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit, if enabled, remains operative
during Sleep mode.
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These periph-
erals include I/O pins that detect a change in the
input signal, WDT, ADC, UART and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC, Timer1 and Input
Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
• The USB module can override the disabling of the
Posc or FRC. Refer to the USB section for
specific details.
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 151