PIC32MX575F256H-80I Datasheet, PDF (84/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

TABLE 4-26:
PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6080
TRISC
31:16
15:0
—
TRISC15
—
TRISC14
—
TRISC13
—
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6090
PORTC
31:16
15:0
—
RC15
—
RC14
—
RC13
—
RC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60A0
LATC
31:16
15:0
—
LATC15
—
LATC14
—
LATC13
—
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60B0
ODCC
31:16
15:0
—
ODCC15
—
ODCC14
—
ODCC13
—
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
F000
0000
xxxx
0000
xxxx
0000
0000
TABLE 4-27:
PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES⁽¹⁾
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6080
TRISC
31:16
15:0
—
TRISC15
—
TRISC14
—
TRISC13
—
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4 TRISC3 TRISC2 TRISC1
—
6090
PORTC
31:16
15:0
—
RC15
—
RC14
—
RC13
—
RC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
60A0
LATC
31:16
15:0
—
LATC15
—
LATC14
—
LATC13
—
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATC4 LATC3 LATC2 LATC1
—
60B0 ODCC
31:16
15:0
—
ODCC15
—
ODCC14
—
ODCC13
—
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCC4 ODCC3 ODCC2 ODCC1
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
F00F
0000
xxxx
0000
xxxx
0000
0000