PIC32MX575F256H-80I Datasheet, PDF (145/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
24.0 ETHERNET CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” in the “PIC32MX Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Following are some of the key features of this module:
• Supports 10/100 Mbps Data Transfer Rates
• Supports Full-Duplex and Half-Duplex Operation
• Supports RMII and MII PHY Interface
• Supports MIIM PHY Management Interface
• Supports both Manual and Automatic Flow Control
• RAM Descriptor-Based DMA Operation for Both
Receive and Transmit Path
• Fully Configurable Interrupts
• Configurable Receive Packet Filtering
- CRC Check
- 64-Byte Pattern Match
- Broadcast, Multicast and Unicast packets
- Magic Packet™
- 64-Bit Hash Table
- Runt Packet
• Supports Packet Payload Checksum Calculation
• Supports Various Hardware Statistics Counters
Figure 24-1 shows a block diagram of the Ethernet
controller.
FIGURE 24-1:
ETHERNET CONTROLLER BLOCK DIAGRAM
TX Bus
Master
TX DMA
TX BM
TX Flow Control
RX DMA
RX BM
RX Bus
Master
RX Filter
Checksum
DMA
Control
Registers
Ethernet DMA
Ethernet Controller
Host IF
TX Function
RX Flow
Control
MII/RMII
IF
MAC
RX Function
MIIM
IF
MAC Control
and
Configuration
Registers
External
PHY
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 145