PIC32MX575F256H-80I Datasheet, PDF (50/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

TABLE 4-2:
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES⁽¹⁾
Bits
31/15 30/14 29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
—
—
—
—
1000 INTCON
15:0
—
FRZ
—
MVEC
—
—
—
—
—
TPC<2:0>
—
—
—
—
—
—
—
SS0 0000
—
—
INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
1010 INTSTAT
15:0
—
—
—
—
—
RIPL<2:0>
—
—
VEC<5:0>
0000
31:16
1020 IPTMR
15:0
IPTMR<31:0>
0000
0000
U1ATXIF U1ARXIF U1AEIF
31:16 I2C1MIF I2CSIF I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF
—
1030 IFS0
—
—
OC5IF
IC5IF
T5IF
INT4IF OC4IF IC4IF T4IF 0000
I2C1AMIF I2C1ASIF I2C1ABIF
15:0 INT3IF OC3IF IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF
—
—
CAN1IF USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
15:0 RTCCIF FSCMIF —
—
U3ATXIF U3ARXIF U3AEIF U2ATXIF U2ARXIF U2AEIF
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
31:16 —
—
—
1050 IFS2
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
U3BTXIF U3BRXIF U3BEIF U2BTXIF U2BRXIF U2BEIF U1BTXIF U1BRXIF U1BEIF PMPEIF IC5EIF IC4EIF 0000
U1ATXIE U1ARXIE U1AEIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C1AMIE I2C1ASIE I2C1ABIE
15:0 INT3IE OC3IE IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE
—
—
CAN1IE USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
15:0 RTCCIE FSCMIE —
—
U3ATXIE U3ARXIE U3AEIE U2ATXIE U2ARXIE U2AEIE
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
31:16 —
—
—
1080 IEC2
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
U3BTXIE U3BRXIE U3BEIE U2BTXIE U2BRXIE U2BEIE U1BTXIE U1BRXIE U1BEIE PMPEIE IC5EIE IC4EIE 0000
31:16 —
—
—
1090 IPC0
15:0
—
—
—
INT0IP<2:0>
CS0IP<2:0>
INT0IS<1:0>
CS0IS<1:0>
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
CS1IS<1:0>
CTIS<1:0>
0000
0000
31:16 —
—
—
10A0 IPC1
15:0
—
—
—
INT1IP<2:0>
IC1IP<2:0>
INT1IS<1:0>
IC1IS<1:0>
—
—
—
—
—
—
OC1IP<2:0>
T1IP<2:0>
OC1IS<1:0>
T1IS<1:0>
0000
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.