PIC32MX575F256H-80I Datasheet, PDF (115/236 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
• 16 Fully Associative Lockable Cache Lines
• 16-Byte Cache Lines
• Up to Four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to Hold
Repeated Instructions
• Pseudo LRU Replacement Policy
• All Cache Lines are Software Writable
• 16-Byte Parallel Memory Fetch
• Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM
CTRL
Bus Ctrl
Cache Ctrl
Prefetch Ctrl
Hit LRU
Miss LRU
Tag Logic
Hit Logic
P_PPrr_reeT_e-F_faFeeg_ett_ctc_chh_h
CTRL
Cache Line
Cache
Line
Address
Encode
P^PPrrer^e-e^FFfe^ettcchh
RDATA
PFM
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 115