PIC16LF1824T39A_12 Datasheet, PDF (93/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
8.5.7 PIR3 REGISTER
The PIR3 register contains the interrupt flag bits, as
shown in Register 8-7.
Note 1: Interrupt flag bits are set when an inter-
rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE, of
the INTCON register. User software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt.
REGISTER 8-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
—
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
—
CCP4IF
CCP3IF TMR6IF
—
TMR4IF
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP4IF: CCP4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CCP3IF: CCP3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 93