PIC16LF1824T39A_12 Datasheet, PDF (265/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

25.6.6 I²C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSP1BUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSP1IF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSP1BUF, leaving SCL low and SDA
unchanged (Figure 25-28).
After the write to the SSP1BUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSP1CON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSP1IF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSP1BUF takes place,
holding SCL low and allowing SDA to float.
25.6.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSP1STAT register
is set when the CPU writes to SSP1BUF and is cleared
when all eight bits are shifted out.
25.6.6.2 WCOL Status Flag
If the user writes the SSP1BUF when a transmit is
already in progress (i.e., SSP1SR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
The WCOL must be cleared by software before the
next transmission.
PIC16LF1824T39A
25.6.6.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSP1CON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
25.6.6.4 Typical Transmit Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSP1CON2 register.
2. SSP1IF is set by hardware on completion of the
Start.
3. SSP1IF is cleared by software.
4. The MSSP1 module will wait the required start
time before any other operation takes place.
5. The user loads the SSP1BUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSP1BUF is written to.
7. The MSSP1 module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSP1CON2 register.
8. The MSSP1 module generates an interrupt at
the end of the ninth clock cycle by setting the
SSP1IF bit.
9. The user loads the SSP1BUF with eight bits of
data.
10. Data is shifted out the SDA pin until all eight bits
are transmitted.
11. The MSSP1 module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSP1CON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSP1CON2 register. Interrupt is generated
once the Stop/Restart condition is complete.
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 265