PIC16LF1824T39A_12 Datasheet, PDF (363/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
FIGURE 31-8:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR and VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33⁽¹⁾
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
TABLE 31-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
30 TMCL MCLR Pulse Width (low)
2 — — s
31 TWDTLP Watchdog Timer
Time-out Period (No Prescaler)
12 16 20 ms VDD = 3.3V-5V
32 TOST Oscillator Start-up Timer Period
(Note 1)
— 1024 — Tosc
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ
I/O high-impedance from MCLR Low —
or Watchdog Timer Reset
— 2.0 s
35 VBOR Brown-out Reset Voltage (Note 2)
36* VHYST Brown-out Reset Hysteresis
2.55 2.70 2.85
1.80 1.9 2.05
20 35 60
V BORV = 0
V BORV = 1
mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response Time 0
1
35 s VDD  VBOR
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 363