PIC16LF1824T39A_12 Datasheet, PDF (264/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
25.6.5 I²C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSP1CON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the
SSP1CON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSP1STAT register will be set. The SSP1IF bit will not
be set until the Baud Rate Generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
FIGURE 25-27: REPEAT START CONDITION WAVEFORM
SDA
Write to SSP1CON2
occurs here
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
and sets SSP1IF
TBRG TBRG TBRG
1st bit
Write to SSP1BUF occurs here
SCL
Sr
Repeated Start
TBRG
TBRG
DS41657A-page 264
Preliminary
 2012 Microchip Technology Inc.