PIC16LF1824T39A_12 Datasheet, PDF (318/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0
—
bit 7
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
CPSCH<3:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1100 =
•
channel 0, (CPS0)
channel 1, (CPS1)
channel 2, (CPS2)
channel 3, (CPS3)
channel 4, (CPS4)
channel 5, (CPS5)
channel 6, (CPS6)
channel 7, (CPS7)
Reserved. Do not use.
•
•
1111 = Reserved. Do not use.
TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
ANSA4
—
ANSA2 ANSA1 ANSA0
ANSELC
—
—
—
—
ANSC3 ANSC2 ANSC1 ANSC0
CPSCON0
CPSON CPSRM
—
—
CPSRNG<1:0>
CPSOUT T0XCS
CPSCON1
—
—
—
—
CPSCH<3:0>
INLVLA
INLVLC
INTCON
—
—
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
—
—
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
IOCIF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PSA
PS2
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
PS1
PS0
—
TMR1ON
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.
Register
on Page
121
127
317
318
122
128
87
173
183
120
126
DS41657A-page 318
Preliminary
 2012 Microchip Technology Inc.