PIC16LF1824T39A_12 Datasheet, PDF (209/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
24.3.7 OPERATION IN SLEEP MODE
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
24.3.8 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
24.3.9 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
24.3.10 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see Section 12.1 “Alternate
Pin Function” for more information.
TABLE 24-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON1
CCPxCON
—
—
PxM<1:0>⁽¹⁾
—
—
DCxB<1:0>
P1DSEL
P1CSEL P2BSEL CCP2SEL
CCPxM<3:0>
CCPTMRS0
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
INLVLA
—
—
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
INLVLC
INTCON
—
—
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
—
—
CCP2IE
PIE3
—
—
CCP4IE CCP3IE TMR6IE
—
TMR4IE
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF
PIR3
—
—
CCP4IF CCP3IF TMR6IF
—
TMR4IF
—
PRx
TxCON
Timer2/4/6 Period Register
—
TxOUTPS<3:0>
TMRxON
TxCKPS<:0>1
TMRx
Timer2/4/6 Module Register
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: Applies to ECCP modules only.
117
224
225
122
128
87
88
89
90
91
92
93
187*
189
187*
120
126
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 209