PIC16LF1824T39A_12 Datasheet, PDF (233/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
FIGURE 25-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCK
SDO
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#1
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
25.2.1 SPI MODE REGISTERS
The MSSP1 module has five registers for SPI mode
operation. These are:
• MSSP1 STATUS Register (SSP1STAT)
• MSSP1 Control Register 1 (SSP1CON1)
• MSSP1 Control Register 3 (SSP1CON3)
• MSSP1 Data Buffer Register (SSP1BUF)
• MSSP1 Address Register (SSP1ADD)
• MSSP1 Shift Register (SSP1SR)
(Not directly accessible)
SSP1CON1 and SSP1STAT are the control and
STATUS registers in SPI mode operation. The
SSP1CON1 register is readable and writable. The
lower six bits of the SSP1STAT are read-only. The
upper two bits of the SSP1STAT are read/write.
In SPI master mode, SSP1ADD can be loaded with a
value used in the Baud Rate Generator. More informa-
tion on the Baud Rate Generator is available in
Section 25.7 “Baud Rate Generator”.
SSP1SR is the shift register used for shifting data in
and out. SSP1BUF provides indirect access to the
SSP1SR register. SSP1BUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSP1SR and SSP1BUF
together create a buffered receiver. When SSP1SR
receives a complete byte, it is transferred to SSP1BUF
and the SSP1IF interrupt is set.
During transmission, the SSP1BUF is not buffered. A
write to SSP1BUF will write to both SSP1BUF and
SSP1SR.
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 233