PIC16LF1824T39A_12 Datasheet, PDF (253/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

25.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSP1CON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSP1IF
interrupt is set.
Figure 25-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSP1IF interrupt is
generated.
4. Slave software clears SSP1IF.
5. Slave software reads ACKTIM bit of SSP1CON3
register, and R/W and D/A of the SSP1STAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSP1BUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSP1CON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSP1IF after the ACK if the R/W bit is
set.
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
SSP1BUF setting the BF bit.
Note: SSP1BUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSP1CON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
PIC16LF1824T39A
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 253