PIC16LF1824T39A_12 Datasheet, PDF (367/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
FIGURE 31-12: PIC16LF1824T39A A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample ^AD132
(TOSC/2 + TCY⁽¹⁾)
AD131
AD130
1 TCY
7
6
54
3
2
1
0
OLD_DATA
Sampling Stopped
NEW_DATA
1 TCY
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 31-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Min. Typ. Max. Units
Comments
CM01
CM02
CM03
CM04A
CM04B
CM04C
CM04D
CM05
CM06
*
Note 1:
2:
VIOFF
Input Offset Voltage
(NOTE 1)
— ±7.5 ±60 mV High-Power mode,
VICM = VDD/2
VICM
Input Common Mode Voltage
0
—
VDD
V
CMRR Common Mode Rejection Ratio — 50 — dB
Response Time Rising Edge
— 400 800 ns High-Power mode
TRESP ^{Response Time Falling Edge}
(NOTE 1) _{Response Time Rising Edge}
— 200 400
— 1200 —
ns High-Power mode
ns Low-Power mode
Response Time Falling Edge
— 550 — ns Low-Power mode
TMC2OV Comparator Mode Change to
Output Valid*
—
—
10
s
CHYSTER Comparator Hysteresis (NOTE 2) —
45
— mV CxHYS = 1
These parameters are characterized but not tested.
High-Power mode only.
Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 367