PIC16LF1824T39A_12 Datasheet, PDF (27/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
100h⁽¹⁾ INDF0
101h⁽¹⁾ INDF1
102h⁽¹⁾
103h⁽¹⁾
104h⁽¹⁾
105h⁽¹⁾
106h⁽¹⁾
107h⁽¹⁾
108h⁽¹⁾
109h⁽¹⁾
10Ah⁽¹⁾
10Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
10Ch LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0 --xx -xxx --uu -uuu
10Eh LATC
—
—
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx uuuu uuuu
10Fh
—
Unimplemented
—
—
110h
—
Unimplemented
—
—
111h CM1CON0
C1ON
C1OUT
C1OE
C1POL
—
C1SP
C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1
C1INTP
C1INTN
C1PCH<1:0>
—
—
C1NCH1 C1NCH0 0000 ---0 0000 ---0
113h CM2CON0
C2ON
C2OUT
C2OE
C2POL
—
C2SP
C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1
C2INTP
C2INTN
C2PCH<1:0>
—
—
C2NCH<1:0>
0000 --00 0000 --00
115h CMOUT
—
—
—
—
—
—
MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON
SBOREN
—
—
—
—
—
—
BORRDY 1--- ---q u--- ---u
117h FVRCON
FVREN FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
118h DACCON0
DACEN DACLPS DACOE
—
DACPSS<1:0>
—
DACNSS 000- 00-0 000- 00-0
119h DACCON1
—
—
—
DACR<4:0>
---0 0000 ---0 0000
11Ah SRCON0
SRLEN
SRCLK<2:0>
SRQEN SRNQEN SRPS
SRPR 0000 0000 0000 0000
11Bh SRCON1
SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch
—
Unimplemented
—
—
11Dh APFCON0
RXDTSEL SDOSEL
SSSEL
—
T1GSEL TXCKSEL
—
—
000- 0000 000- 0000
11Eh APFCON1
—
—
—
—
P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000
11Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 27