PIC16LF1824T39A_12 Datasheet, PDF (203/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
PIC16LF1824T39A
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see Section 12.1 “Alternate
Pin Function” for more information.
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON1
CCPxCON
—
—
PxM<1:0>⁽¹⁾
—
—
DCxB<1:0>
P1DSEL
P1CSEL P2BSEL CCP2SEL
CCPxM<3:0>
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)
CCPRxH Capture/Compare/PWM Register x High Byte (MSB)
CMxCON0 CxON
CxOUT
CxOE
CxPOL
—
CxSP
CxHYS CxSYNC
CMxCON1 CxINTP CxINTN
CxPCH<1:0>
—
—
CxNCH<1:0>
INLVLA
—
—
INLVLA5 INLVLA4
INLVLA3
INLVLA2 INLVLA1 INLVLA0
INLVLC
INTCON
—
—
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE
CCP1IE TMR2IE TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
—
—
CCP2IE
PIE3
PIR1
—
TMR1GIF
—
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR6IE
SSP1IF
—
CCP1IF
TMR4IE
TMR2IF
—
TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF
PIR3
T1CON
—
—
CCP4IF CCP3IF
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0
TMR6IF
T1OSCEN
—
T1SYNC
TMR4IF
—
—
TMR1ON
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA
—
—
TRISA5 TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
TRISC
—
—
TRISC5 TRISC4
TRISC3
TRISC2 TRISC1
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by the Capture.
* Page provides register information.
Note 1: Applies to ECCP modules only.
TRISC0
Register
on Page
117
224
202*
202*
168
169
122
128
87
88
89
90
91
92
93
183
184
179*
179*
120
126
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 203