PIC16LF1824T39A_12 Datasheet, PDF (240/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP1 clock is much faster than the system clock.
In Slave mode, when MSSP1 interrupts are enabled,
after the master completes sending data, an MSSP1
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP1
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP1 interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSELC
—
—
—
—
ANSC3
ANSC2
ANSC1
APFCON0
RXDTSEL SDOSEL
SSSEL
—
T1GSEL
TXCKSEL
—
INLVLA
—
—
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLC
—
—
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
SSP1CON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISC
—
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
* Page provides register information.
ANSA0
ANSC0
—
INLVLA0
INLVLC0
IOCIF
TMR1IE
TMR1IF
DHEN
BF
TRISA0
TRISC0
Register on
Page
121
127
116
122
128
87
88
91
233*
279
281
278
120
126
DS41657A-page 240
Preliminary
 2012 Microchip Technology Inc.