PIC16LF1824T39A_12 Datasheet, PDF (307/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON0
RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL
—
—
BAUDCON
ABDOVF RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
SPBRGL
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
SPBRGH
BRG15
BRG14 BRG13 BRG12 BRG11 BRG10
BRG9
BRG8
TXSTA
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
116
294
87
88
91
288*
293
295*
295*
292
 2012 Microchip Technology Inc.
Preliminary
DS41657A-page 307