PIC16LF1824T39A_12 Datasheet, PDF (260/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
25.5.8 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I²C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I²C protocol, defined as address 0x00. When the
GCEN bit of the SSP1CON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSP1ADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSP1BUF and respond.
Figure 25-24 shows a general call reception
sequence.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSP1CON3 register is set, just
as with any other address reception, the slave hard-
ware will stretch the clock after the 8th falling edge of
SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
FIGURE 25-24:
SDA
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
General Call Address
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
Receiving Data
ACK
ACK _{D7 D6 D5 D4 D3 D2 D1 D0}
SCL
SSP1IF
S
1 2 34 5 6 78 91 2 34 5 6 78 9
BF (SSP1STAT<0>)
GCEN (SSP1CON2<7>)
Cleared by software
SSP1BUF is read
’1’
25.5.9 SSP1 MASK REGISTER
An SSP1 Mask (SSP1MSK) register (Register 25-5) is
available in I²C Slave mode as a mask for the value
held in the SSP1SR register during an address
comparison operation. A zero (‘0’) bit in the SSP1MSK
register has the effect of making the corresponding bit
of the received address a “don’t care.”
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP1 operation until written with a mask value.
The SSP1 Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP1 mask has no effect during the
reception of the first (high) byte of the address.
DS41657A-page 260
Preliminary
 2012 Microchip Technology Inc.