PIC16LF1824T39A_12 Datasheet, PDF (412/418 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with XLP Technology

PIC16LF1824T39A
TMR1H Register ....................................................... 175
TMR1L Register ........................................................ 175
Timer2
Associated registers.................................................. 190
Timer2/4/6 ......................................................................... 187
Associated registers.................................................. 190
Timers
Timer1
T1CON.............................................................. 183
T1GCON ........................................................... 184
Timer2/4/6
TXCON ............................................................. 189
Timing Diagrams
A/D Conversion ......................................................... 366
A/D Conversion (Sleep Mode) .................................. 367
Acknowledge Sequence ........................................... 269
Asynchronous Reception .......................................... 290
Asynchronous Transmission ..................................... 286
Asynchronous Transmission (Back to Back) ............ 287
Auto Wake-up Bit (WUE) During Normal Operation . 302
Auto Wake-up Bit (WUE) During Sleep .................... 302
Automatic Baud Rate Calibration .............................. 300
Baud Rate Generator with Clock Arbitration ............. 262
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 273
Brown-out Reset (BOR) ............................................ 363
Brown-out Reset Situations ........................................ 73
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 274
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 274
Bus Collision During a Start Condition (SCL = 0) ..... 273
Bus Collision During a Stop Condition (Case 1) ....... 275
Bus Collision During a Stop Condition (Case 2) ....... 275
Bus Collision During Start Condition (SDA only) ...... 272
Bus Collision for Transmit and Acknowledge............ 271
CLKOUT and I/O....................................................... 361
Clock Synchronization .............................................. 259
Clock Timing ............................................................. 360
Comparator Output ................................................... 163
Enhanced Capture/Compare/PWM (ECCP) ............. 365
Fail-Safe Clock Monitor (FSCM) ................................. 63
First Start Bit Timing ................................................. 263
Full-Bridge PWM Output ........................................... 215
Half-Bridge PWM Output .................................. 213, 220
I²C Bus Data ............................................................. 373
I²C Bus Start/Stop Bits.............................................. 372
I²C Master Mode (7 or 10-Bit Transmission) ............ 266
I²C Master Mode (7-Bit Reception) ........................... 268
I²C Stop Condition Receive or Transmit Mode ......... 270
INT Pin Interrupt.......................................................... 85
Internal Oscillator Switch Timing................................. 58
PWM Auto-shutdown ................................................ 219
Firmware Restart .............................................. 218
PWM Direction Change ............................................ 216
PWM Direction Change at Near 100% Duty Cycle ... 217
PWM Output (Active-High)........................................ 211
PWM Output (Active-Low) ........................................ 212
Repeat Start Condition.............................................. 264
Reset Start-up Sequence............................................ 76
Reset, WDT, OST and Power-up Timer ................... 362
Send Break Character Sequence ............................. 303
SPI Master Mode (CKE = 1, SMP = 1) ..................... 370
SPI Mode (Master Mode) .......................................... 236
SPI Slave Mode (CKE = 0) ....................................... 370
SPI Slave Mode (CKE = 1) ....................................... 371
Synchronous Reception (Master Mode, SREN) ....... 307
Synchronous Transmission ...................................... 305
Synchronous Transmission (Through TXEN) ........... 305
Timer0 and Timer1 External Clock ........................... 364
Timer1 Incrementing Edge ....................................... 179
Two Speed Start-up.................................................... 61
USART Synchronous Receive (Master/Slave) ......... 368
USART Synchronous Transmission (Master/Slave). 368
Wake-up from Interrupt............................................... 96
Timing Diagrams and Specifications
PLL Clock ................................................................. 361
Timing Parameter Symbology .......................................... 359
Timing Requirements
I²C Bus Data............................................................. 374
SPI Mode .................................................................. 372
TINLVLC Register............................................................. 128
TMR0 Register.................................................................... 25
TMR1H Register ................................................................. 25
TMR1L Register.................................................................. 25
TMR2 Register.................................................................... 25
TMR4 Register.................................................................... 33
TMR6 Register.................................................................... 33
TRIS.................................................................................. 348
TRISA Register........................................................... 26, 120
TRISC Register........................................................... 26, 126
Two-Speed Clock Start-up Mode........................................ 60
TXCON (Timer2/4/6) Register .......................................... 189
TXREG ............................................................................. 285
TXREG Register ................................................................. 28
TXSTA Register.......................................................... 28, 292
BRGH Bit .................................................................. 295
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 368
Requirements, Synchronous Transmission...... 368
Timing Diagram, Synchronous Receive ........... 368
Timing Diagram, Synchronous Transmission... 368
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 301
Wake-up Using Interrupts ................................................... 95
Watchdog Timer (WDT)...................................................... 75
Modes ......................................................................... 98
Specifications ........................................................... 363
WCOL ....................................................... 262, 265, 267, 269
WCOL Status Flag.................................... 262, 265, 267, 269
WDTCON Register ............................................................. 99
WPUA Register................................................................. 122
WPUC Register ................................................................ 128
Write Protection .................................................................. 47
WWW Address ................................................................. 413
WWW, On-Line Support ....................................................... 6
DS41657A-page 412
Preliminary
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